Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Wait for the completion of DMA operations during writes | Suren A. Chilingaryan | 2011-07-11 | 1 | -319/+39 |
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* | IRQ support in NWL DMA engine | Suren A. Chilingaryan | 2011-07-11 | 1 | -93/+26 |
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* | Support dynamic registers, support register offsets and multiregisters ↵ | Suren A. Chilingaryan | 2011-07-09 | 1 | -8/+67 |
| | | | | (bitmasks), list NWL DMA registers | ||||
* | Add some check to verify if NWL DMA engine have been successfully initialized | Suren A. Chilingaryan | 2011-07-08 | 1 | -5/+3 |
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* | Support alignments in kmem allocation | Suren A. Chilingaryan | 2011-07-06 | 1 | -1/+1 |
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* | A bit of renaming | Suren A. Chilingaryan | 2011-07-06 | 1 | -9/+9 |
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* | Define addresses of NWL engines | root | 2011-07-04 | 1 | -1/+3 |
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* | North West Logick DMA implementation | root | 2011-07-04 | 1 | -102/+560 |
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* | DMA engine initialization and basic intrastructure for DMA read/write | root | 2011-06-18 | 1 | -0/+98 |
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* | Enumerate DMA engines | root | 2011-06-17 | 1 | -0/+178 |