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* Image frames decodingSuren A. Chilingaryan2011-12-091-1/+1
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* new event architecture, first trialSuren A. Chilingaryan2011-12-081-3/+4
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* Separate NWL loopback code, provide DMA start/stop interfacesSuren A. Chilingaryan2011-07-121-1/+1
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* Another reorganization of NWL sourcesSuren A. Chilingaryan2011-07-121-1/+1
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* IRQ support in NWL DMA engineSuren A. Chilingaryan2011-07-111-1/+1
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* Support FIFO reading/writting, code restructurization, few fixesSuren A. Chilingaryan2011-07-061-1/+1
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* North West Logick DMA implementationroot2011-07-041-1/+1
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* Enumerate DMA enginesroot2011-06-171-1/+1
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* Look for headers in the current directorySuren A. Chilingaryan2011-04-121-1/+1
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* Infrastructure for event APISuren A. Chilingaryan2011-04-121-1/+2
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* install scriptSuren A. Chilingaryan2011-03-141-0/+7
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* Support for FPGA registersSuren A. Chilingaryan2011-03-091-1/+1
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* Initial support for registers, infrastructure onlySuren A. Chilingaryan2011-02-181-3/+7
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* Initial importSuren A. Chilingaryan2011-02-131-0/+26