Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Image frames decoding | Suren A. Chilingaryan | 2011-12-09 | 1 | -1/+1 |
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* | new event architecture, first trial | Suren A. Chilingaryan | 2011-12-08 | 1 | -3/+4 |
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* | Separate NWL loopback code, provide DMA start/stop interfaces | Suren A. Chilingaryan | 2011-07-12 | 1 | -1/+1 |
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* | Another reorganization of NWL sources | Suren A. Chilingaryan | 2011-07-12 | 1 | -1/+1 |
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* | IRQ support in NWL DMA engine | Suren A. Chilingaryan | 2011-07-11 | 1 | -1/+1 |
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* | Support FIFO reading/writting, code restructurization, few fixes | Suren A. Chilingaryan | 2011-07-06 | 1 | -1/+1 |
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* | North West Logick DMA implementation | root | 2011-07-04 | 1 | -1/+1 |
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* | Enumerate DMA engines | root | 2011-06-17 | 1 | -1/+1 |
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* | Look for headers in the current directory | Suren A. Chilingaryan | 2011-04-12 | 1 | -1/+1 |
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* | Infrastructure for event API | Suren A. Chilingaryan | 2011-04-12 | 1 | -1/+2 |
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* | install script | Suren A. Chilingaryan | 2011-03-14 | 1 | -0/+7 |
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* | Support for FPGA registers | Suren A. Chilingaryan | 2011-03-09 | 1 | -1/+1 |
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* | Initial support for registers, infrastructure only | Suren A. Chilingaryan | 2011-02-18 | 1 | -3/+7 |
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* | Initial import | Suren A. Chilingaryan | 2011-02-13 | 1 | -0/+26 |