Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Big redign of model structures | Suren A. Chilingaryan | 2015-04-20 | 1 | -7/+5 |
| | |||||
* | multithread preprocessing of ipecamera frames and code reorganization | Suren A. Chilingaryan | 2011-12-12 | 1 | -0/+1 |
| | |||||
* | Gathering a bit of statistics | Suren A. Chilingaryan | 2011-12-09 | 1 | -0/+1 |
| | |||||
* | Initial support of event streaming in cli | Suren A. Chilingaryan | 2011-12-09 | 1 | -3/+6 |
| | |||||
* | new event architecture, first trial | Suren A. Chilingaryan | 2011-12-08 | 1 | -0/+5 |
| | |||||
* | Implement DMA access synchronization for NWL implementation | Suren A. Chilingaryan | 2011-07-17 | 1 | -2/+1 |
| | |||||
* | Implement DMA access synchronization in the driver | Suren A. Chilingaryan | 2011-07-16 | 1 | -0/+7 |
| | |||||
* | Suppport DMA modes in console application (not functional yet) | Suren A. Chilingaryan | 2011-07-12 | 1 | -0/+2 |
| | |||||
* | Support FIFO reading/writting, code restructurization, few fixes | Suren A. Chilingaryan | 2011-07-06 | 1 | -0/+2 |
| | |||||
* | North West Logick DMA implementation | root | 2011-07-04 | 1 | -0/+2 |
| | |||||
* | clean up | Suren A. Chilingaryan | 2011-04-12 | 1 | -1/+1 |
| | |||||
* | Support for FPGA registers | Suren A. Chilingaryan | 2011-03-09 | 1 | -0/+3 |
| | |||||
* | Initial support of IPECamera protocol | Suren A. Chilingaryan | 2011-03-08 | 1 | -4/+16 |
| | |||||
* | Initial support for registers, infrastructure only | Suren A. Chilingaryan | 2011-02-18 | 1 | -1/+4 |
| | |||||
* | Print a bit more details | Suren A. Chilingaryan | 2011-02-13 | 1 | -0/+1 |
| | |||||
* | Initial import | Suren A. Chilingaryan | 2011-02-13 | 1 | -0/+5 |