Fix temperature register of ipecamera and prepend all cmosis registers with _cmosis prefix

3 files changed, 61 insertions, 60 deletions

diff --git a/ipecamera/ipecamera.c b/ipecamera/ipecamera.c
index 4ed2c5f..0710f4d 100644
--- a/ipecamera/ipecamera.c
+++ b/ipecamera/ipecamera.c
@@ -60,8 +60,8 @@
 	if (err) { \
 	    pcilib_error("Error reading %s register", ipecamera_registers[ctx->reg].name); \
 	} \
-	if (!(check)) { \
-	    pcilib_error("Unexpected value (%li) of register %s", value, ipecamera_registers[ctx->reg].name); \
+	if (value != check) { \
+	    pcilib_error("Unexpected value (0x%lx) of register %s", value, ipecamera_registers[ctx->reg].name); \
 	    err = PCILIB_ERROR_INVALID_DATA; \
 	} \
     }
@@ -98,10 +98,10 @@ pcilib_context_t *ipecamera_init(pcilib_t *pcilib) {
 
 	FIND_REG(status3_reg, "fpga", "status3");
 
-	FIND_REG(n_lines_reg, "cmosis", "number_lines");
-	FIND_REG(line_reg, "cmosis", "start1");
-	FIND_REG(exposure_reg, "cmosis", "exp_time");
-	FIND_REG(flip_reg, "cmosis", "image_flipping");
+	FIND_REG(n_lines_reg, "cmosis", "cmosis_number_lines");
+	FIND_REG(line_reg, "cmosis", "cmosis_start1");
+	FIND_REG(exposure_reg, "cmosis", "cmosis_exp_time");
+	FIND_REG(flip_reg, "cmosis", "cmosis_image_flipping");
 	
 	FIND_REG(adc_resolution_reg, "fpga", "adc_resolution");
 	FIND_REG(output_mode_reg, "fpga", "output_mode");
@@ -472,7 +472,7 @@ int ipecamera_start(pcilib_context_t *vctx, pcilib_event_t event_mask, pcilib_ev
 	sched.sched_priority = sched_get_priority_max(SCHED_FIFO) - 1;	// Let 1 priority for something really critcial
 	pthread_attr_setschedparam(&attr, &sched);
     }
-    
+
     if (pthread_create(&ctx->rthread, &attr, &ipecamera_reader_thread, (void*)ctx)) {
 	ctx->started = 0;
 	ipecamera_stop(vctx, PCILIB_EVENT_FLAGS_DEFAULT);
@@ -603,7 +603,7 @@ int ipecamera_trigger(pcilib_context_t *vctx, pcilib_event_t event, size_t trigg
     
     SET_REG(control_reg, IPECAMERA_FRAME_REQUEST|IPECAMERA_READOUT_FLAG);
     usleep(IPECAMERA_WAIT_FRAME_RCVD_TIME);
-    CHECK_REG(status_reg, IPECAMERA_EXPECTED_STATUS);
+    //CHECK_REG(status_reg, IPECAMERA_EXPECTED_STATUS);
     SET_REG(control_reg, IPECAMERA_IDLE|IPECAMERA_READOUT_FLAG);
 
 
diff --git a/ipecamera/model.h b/ipecamera/model.h
index 3899acc..9034e59 100644
--- a/ipecamera/model.h
+++ b/ipecamera/model.h
@@ -26,51 +26,51 @@ pcilib_register_bank_description_t ipecamera_register_banks[] = {
 };
 
 pcilib_register_description_t ipecamera_registers[] = {
-{1, 	0, 	16, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines",  ""},
-{3, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start1", ""},
-{5, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start2", ""},
-{7, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start3", ""},
-{9, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start4", ""},
-{11,	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start5", ""},
-{13, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start6", ""},
-{15, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start7", ""},
-{17, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "start8", ""},
-{19, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines1", ""},
-{21, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines2", ""},
-{23, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines3", ""},
-{25, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines4", ""},
-{27, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines5", ""},
-{29, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines6", ""},
-{31, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines7", ""},
-{33, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_lines8", ""},
-{35, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "sub_s", ""},
-{37, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "sub_a", ""},
-{39, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "color", ""},
-{40, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "image_flipping", ""},
-{41, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_flags", ""},
-{42, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_time", ""},
-{45, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_step", ""},
-{48, 	0, 	24, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_kp1", ""},
-{51, 	0, 	24, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_kp2", ""},
-{54, 	0, 	2, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "nr_slopes", ""},
-{55, 	0, 	8, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_seq", ""},
-{56, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_time2", ""},
-{59, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_step2", ""},
-{68, 	0, 	2, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "nr_slopes2", ""},
-{69, 	0, 	8, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "exp_seq2", ""},
-{70, 	0, 	16, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "number_frames", ""},
-{72, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "output_mode", ""},
-{78, 	0, 	12, 	85, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "training_pattern", ""},
-{80, 	0, 	18, 	0x3FFFF,0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "channel_en", ""},
-{82, 	0, 	3, 	7, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "special_82", ""},
-{89, 	0, 	8, 	96, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "vlow2", ""},
-{90, 	0, 	8, 	96, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "vlow3", ""},
-{100, 	0, 	14, 	16260, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "offset", ""},
-{102, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "pga", ""},
-{103, 	0, 	8, 	32, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "adc_gain", ""},
-{111, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "bit_mode", ""},
-{112, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "adc_resolution", ""},
-{115, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "special_115", ""},
+{1, 	0, 	16, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines",  ""},
+{3, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start1", ""},
+{5, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start2", ""},
+{7, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start3", ""},
+{9, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start4", ""},
+{11,	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start5", ""},
+{13, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start6", ""},
+{15, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start7", ""},
+{17, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start8", ""},
+{19, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines1", ""},
+{21, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines2", ""},
+{23, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines3", ""},
+{25, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines4", ""},
+{27, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines5", ""},
+{29, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines6", ""},
+{31, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines7", ""},
+{33, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines8", ""},
+{35, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_s", ""},
+{37, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_a", ""},
+{39, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_color", ""},
+{40, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_image_flipping", ""},
+{41, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_flags", ""},
+{42, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time", ""},
+{45, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step", ""},
+{48, 	0, 	24, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp1", ""},
+{51, 	0, 	24, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp2", ""},
+{54, 	0, 	2, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""},
+{55, 	0, 	8, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq", ""},
+{56, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time2", ""},
+{59, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step2", ""},
+{68, 	0, 	2, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes2", ""},
+{69, 	0, 	8, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq2", ""},
+{70, 	0, 	16, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_frames", ""},
+{72, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_output_mode", ""},
+{78, 	0, 	12, 	85, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_training_pattern", ""},
+{80, 	0, 	18, 	0x3FFFF,0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_channel_en", ""},
+{82, 	0, 	3, 	7, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_82", ""},
+{89, 	0, 	8, 	96, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow2", ""},
+{90, 	0, 	8, 	96, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow3", ""},
+{100, 	0, 	14, 	16260, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_offset", ""},
+{102, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_pga", ""},
+{103, 	0, 	8, 	32, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_gain", ""},
+{111, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_bit_mode", ""},
+{112, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_resolution", ""},
+{115, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_115", ""},
 /*{126, 	0, 	16, 	0, 	PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "temp", ""},*/
 {0x00,	0, 	32,	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
 {0x10,	0, 	32,	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
@@ -97,18 +97,19 @@ pcilib_register_description_t ipecamera_registers[] = {
 {0xc0,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "skiped_lines", ""},
 {0x100,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rawdata_pkt_addr", ""},
 {0x110,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_info", ""},
-{0x110,	0, 	19, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature",  ""},
+{0x110,	0, 	16, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature",  ""},
+{0x110,	16, 	3, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature_alarms",  ""},
 {0x110,	19, 	10, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature",  ""},
-{0x110,	29, 	3, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "temperature_alarms",  ""},
-{0x120,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "copy_num_lines", ""},
-{0x130,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "copy_start_line", ""},
-{0x140,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "copy_exp_time", ""},
+{0x110,	29, 	3, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature_alarms",  ""},
+{0x120,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_lines", ""},
+{0x130,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_line", ""},
+{0x140,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "exp_time", ""},
 {0x150,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "motor", ""},
 {0x150,	0, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_phi",  ""},
 {0x150,	5, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_z",  ""},
 {0x150,	10, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_y",  ""},
 {0x150,	15, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_x",  ""},
-{0x150,	20, 	8, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "copy_adc_gain",  ""},
+{0x150,	20, 	8, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_gain",  ""},
 {0x160,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "write_status", ""},
 {0x170,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_triggers", ""},
 {0x180,	0, 	32, 	0x280,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "trigger_period", ""},
diff --git a/ipecamera/private.h b/ipecamera/private.h
index 2851515..5dc10d1 100644
--- a/ipecamera/private.h
+++ b/ipecamera/private.h
@@ -18,7 +18,7 @@
 #define IPECAMERA_NOFRAME_PREPROC_SLEEP 100
 
 #define IPECAMERA_MAX_LINES 1088
-#define IPECAMERA_EXPECTED_STATUS 0x08409FFFF
+#define IPECAMERA_EXPECTED_STATUS 0x08449FFFF
 #define IPECAMERA_END_OF_SEQUENCE 0x1F001001
 
 #define IPECAMERA_MAX_CHANNELS 16