Add frame-reject registers to IPECamera model

2 files changed, 101 insertions, 92 deletions

diff --git a/ipecamera/model.h b/ipecamera/model.h
index 4c527df..26505ee 100644
--- a/ipecamera/model.h
+++ b/ipecamera/model.h
@@ -26,97 +26,102 @@ pcilib_register_bank_description_t ipecamera_register_banks[] = {
 };
 
 pcilib_register_description_t ipecamera_registers[] = {
-{1, 	0, 	16, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines",  ""},
-{3, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start1", ""},
-{5, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start2", ""},
-{7, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start3", ""},
-{9, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start4", ""},
-{11,	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start5", ""},
-{13, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start6", ""},
-{15, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start7", ""},
-{17, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start8", ""},
-{19, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines1", ""},
-{21, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines2", ""},
-{23, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines3", ""},
-{25, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines4", ""},
-{27, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines5", ""},
-{29, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines6", ""},
-{31, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines7", ""},
-{33, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines8", ""},
-{35, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_s", ""},
-{37, 	0, 	16, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_a", ""},
-{39, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_color", ""},
-{40, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_image_flipping", ""},
-{41, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_flags", ""},
-{42, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time", ""},
-{45, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step", ""},
-{48, 	0, 	24, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp1", ""},
-{51, 	0, 	24, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp2", ""},
-{54, 	0, 	2, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""},
-{55, 	0, 	8, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq", ""},
-{56, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time2", ""},
-{59, 	0, 	24, 	1088, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step2", ""},
-{68, 	0, 	2, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes2", ""},
-{69, 	0, 	8, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq2", ""},
-{70, 	0, 	16, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_frames", ""},
-{72, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_output_mode", ""},
-{78, 	0, 	12, 	85, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_training_pattern", ""},
-{80, 	0, 	18, 	0x3FFFF,0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_channel_en", ""},
-{82, 	0, 	3, 	7, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_82", ""},
-{89, 	0, 	8, 	96, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow2", ""},
-{90, 	0, 	8, 	96, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow3", ""},
-{100, 	0, 	14, 	16260, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_offset", ""},
-{102, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_pga", ""},
-{103, 	0, 	8, 	32, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_gain", ""},
-{111, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_bit_mode", ""},
-{112, 	0, 	2, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_resolution", ""},
-{115, 	0, 	1, 	1, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_115", ""},
-/*{126, 	0, 	16, 	0, 	PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "temp", ""},*/
-{0x00,	0, 	32,	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
-{0x10,	0, 	32,	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
-{0x20,	0, 	32,	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
-{0x30,	0, 	32,	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_info", ""},
-{0x30, 	0, 	8, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_version",  ""},
-{0x30, 	8, 	1, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_bitmode",  ""},
-{0x30, 	12, 	2, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_resolution",  ""},
-{0x30, 	16, 	2, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "output_mode",  ""},
-{0x40,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "control", ""},
-{0x50,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status", ""},
-{0x54,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status2", ""},
-{0x58,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status3", ""},
-{0x5c,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_status", ""},
-{0x70,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_address", ""},
-{0x74,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "end_address", ""},
-{0x78,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rd_address", ""},
-{0xa0,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param1", ""},
-{0xa0, 	0, 	11, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_skip_lines",  ""},
-{0xa0, 	11, 	11, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_num_lines",  ""},
-{0xa0, 	22, 	10, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_start_address",  ""},
-{0xb0,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param2", ""},
-{0xa0, 	0, 	11, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_threshold_lines",  ""},
-{0xc0,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "skiped_lines", ""},
-{0x100,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rawdata_pkt_addr", ""},
-{0x110,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_info", ""},
-{0x110,	0, 	16, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature",  ""},
-{0x110,	16, 	3, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature_alarms",  ""},
-{0x110,	19, 	10, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature",  ""},
-{0x110,	29, 	3, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature_alarms",  ""},
-{0x120,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_lines", ""},
-{0x130,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_line", ""},
-{0x140,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "exp_time", ""},
-{0x150,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "motor", ""},
-{0x150,	0, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_phi",  ""},
-{0x150,	5, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_z",  ""},
-{0x150,	10, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_y",  ""},
-{0x150,	15, 	5, 	0, 	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_x",  ""},
-{0x150,	20, 	8, 	0, 	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_gain",  ""},
-{0x160,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "write_status", ""},
-{0x170,	0, 	32, 	0,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_triggers", ""},
-{0x180,	0, 	32, 	0x280,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "trigger_period", ""},
-{0x190,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_sample_period", ""},
-{0x1a0,	0, 	32, 	0x64,	0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_max_frames", ""},
-{0x1b0,	0, 	32, 	0,	0, PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_num_frames", ""},
-{0,	0,	0,	0,	0, 0,                  0,                        0,                     NULL, NULL}
+{1, 	0, 	16, 	1088, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines",  ""},
+{3, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start1", ""},
+{5, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start2", ""},
+{7, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start3", ""},
+{9, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start4", ""},
+{11,	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start5", ""},
+{13, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start6", ""},
+{15, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start7", ""},
+{17, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_start8", ""},
+{19, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines1", ""},
+{21, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines2", ""},
+{23, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines3", ""},
+{25, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines4", ""},
+{27, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines5", ""},
+{29, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines6", ""},
+{31, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines7", ""},
+{33, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_lines8", ""},
+{35, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_s", ""},
+{37, 	0, 	16, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_sub_a", ""},
+{39, 	0, 	1, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_color", ""},
+{40, 	0, 	2, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_image_flipping", ""},
+{41, 	0, 	2, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_flags", ""},
+{42, 	0, 	24, 	1088, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time", ""},
+{45, 	0, 	24, 	1088, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step", ""},
+{48, 	0, 	24, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp1", ""},
+{51, 	0, 	24, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_kp2", ""},
+{54, 	0, 	2, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes", ""},
+{55, 	0, 	8, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq", ""},
+{56, 	0, 	24, 	1088, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_time2", ""},
+{59, 	0, 	24, 	1088, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_step2", ""},
+{68, 	0, 	2, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_nr_slopes2", ""},
+{69, 	0, 	8, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_exp_seq2", ""},
+{70, 	0, 	16, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_number_frames", ""},
+{72, 	0, 	2, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_output_mode", ""},
+{78, 	0, 	12, 	85, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_training_pattern", ""},
+{80, 	0, 	18, 	0x3FFFF,0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_channel_en", ""},
+{82, 	0, 	3, 	7, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_82", ""},
+{89, 	0, 	8, 	96, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow2", ""},
+{90, 	0, 	8, 	96, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_vlow3", ""},
+{100, 	0, 	14, 	16260, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_offset", ""},
+{102, 	0, 	2, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_pga", ""},
+{103, 	0, 	8, 	32, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_gain", ""},
+{111, 	0, 	1, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_bit_mode", ""},
+{112, 	0, 	2, 	0, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_adc_resolution", ""},
+{115, 	0, 	1, 	1, 	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "cmosis_special_115", ""},
+/*{126, 	0, 	16, 	0,                        	PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "temp", ""},*/
+{0x00,	0, 	32,	0,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
+{0x10,	0, 	32,	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
+{0x20,	0, 	32,	0,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
+{0x30,	0, 	32,	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_info", ""},
+{0x30, 	0, 	8, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_version",  ""},
+{0x30, 	8, 	1, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "firmware_bitmode",  ""},
+{0x30, 	12, 	2, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_resolution",  ""},
+{0x30, 	16, 	2, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "output_mode",  ""},
+{0x40,	0, 	32, 	0,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "control", ""},
+{0x50,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status", ""},
+{0x54,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status2", ""},
+{0x58,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status3", ""},
+{0x5c,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_status", ""},
+{0x70,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_address", ""},
+{0x74,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "end_address", ""},
+{0x78,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rd_address", ""},
+{0xa0,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param1", ""},
+{0xa0, 	0, 	10, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_skip_lines",  ""},
+{0xa0, 	10, 	11, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_num_lines",  ""},
+{0xa0, 	21, 	11, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_start_address",  ""},
+{0xb0,	0, 	32, 	0,	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param2", ""},
+{0xb0, 	0, 	11, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_threshold_start_line",  ""},
+{0xb0, 	16, 	10, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fr_area_lines",  ""},
+{0xc0,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "skiped_lines", ""},
+{0xd0,	0, 	32, 	0,	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_thresholds", ""},
+{0xd0,	0, 	10, 	0,	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_pixel_thr", ""},
+{0xd0,	10, 	11, 	0,	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_pixel_thr", ""},
+{0xd0,	21, 	11, 	0,	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_num_lines_thr", ""},
+{0x100,	0, 	32, 	0,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rawdata_pkt_addr", ""},
+{0x110,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_info", ""},
+{0x110,	0, 	16, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature",  ""},
+{0x110,	16, 	3, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "sensor_temperature_alarms",  ""},
+{0x110,	19, 	10, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature",  ""},
+{0x110,	29, 	3, 	0, 	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "fpga_temperature_alarms",  ""},
+{0x120,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_lines", ""},
+{0x130,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_line", ""},
+{0x140,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "exp_time", ""},
+{0x150,	0, 	32, 	0,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "motor", ""},
+{0x150,	0, 	5, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_phi",  ""},
+{0x150,	5, 	5, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_z",  ""},
+{0x150,	10, 	5, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_y",  ""},
+{0x150,	15, 	5, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "motor_x",  ""},
+{0x150,	20, 	8, 	0, 	PCILIB_REGISTER_ALL_BITS, PCILIB_REGISTER_R,  PCILIB_REGISTER_BITS,     PCILIB_REGISTER_BANK1, "adc_gain",  ""},
+{0x160,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "write_status", ""},
+{0x170,	0, 	32, 	0,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_triggers", ""},
+{0x180,	0, 	32, 	0x280,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "trigger_period", ""},
+{0x190,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_sample_period", ""},
+{0x1a0,	0, 	32, 	0x64,	0,                        PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_max_frames", ""},
+{0x1b0,	0, 	32, 	0,	0,                        PCILIB_REGISTER_R,  PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "ddr_num_frames", ""},
+{0,	0,	0,	0,	0,                        0,                  0,                        0,                     NULL, NULL}
 };
 
 pcilib_register_range_t ipecamera_register_ranges[] = {
diff --git a/pcilib.h b/pcilib.h
index dfe4b6c..4df7f1a 100644
--- a/pcilib.h
+++ b/pcilib.h
@@ -130,6 +130,8 @@ typedef enum {
 #define PCILIB_TIMEOUT_IMMEDIATE	0
 #define PCILIB_IRQ_TYPE_ALL 		0
 #define PCILIB_IRQ_SOURCE_DEFAULT	0
+#define PCILIB_REGISTER_NO_BITS		0
+#define PCILIB_REGISTER_ALL_BITS	((pcilib_register_value_t)-1)
 
 typedef struct {
     pcilib_event_t type;
@@ -183,7 +185,9 @@ typedef struct {
     pcilib_register_size_t offset;
     pcilib_register_size_t bits;
     pcilib_register_value_t defvalue;
-    pcilib_register_value_t rwmask;	/**< 1 - read before write bits, 0 - zero should be written to preserve value */
+    pcilib_register_value_t rwmask;	/**< 1 - read before write bits, 0 - zero should be written to preserve value 
+					Used to define how external bits of PCILIB_REGISTER_BITS registers are treated.
+					Currently it is a bit confusing, we may find a better way in the next release */
     pcilib_register_mode_t mode;
     pcilib_register_type_t type;