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author | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-11 01:37:54 +0200 |
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committer | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-11 01:37:54 +0200 |
commit | c095f06560a0efacc7a34ea4e7f1e69c1faab0cf (patch) | |
tree | c005686153325eadb3d5c97617154f0acba75fbb /dma/nwl_register.h | |
parent | 02924fc49641ca9c000054a7a540b6f1eaa0e8f8 (diff) | |
download | ipecamera-c095f06560a0efacc7a34ea4e7f1e69c1faab0cf.tar.gz ipecamera-c095f06560a0efacc7a34ea4e7f1e69c1faab0cf.tar.bz2 ipecamera-c095f06560a0efacc7a34ea4e7f1e69c1faab0cf.tar.xz ipecamera-c095f06560a0efacc7a34ea4e7f1e69c1faab0cf.zip |
IRQ support in NWL DMA engine
Diffstat (limited to 'dma/nwl_register.h')
-rw-r--r-- | dma/nwl_register.h | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/dma/nwl_register.h b/dma/nwl_register.h index 86515cc..bffc1bf 100644 --- a/dma/nwl_register.h +++ b/dma/nwl_register.h @@ -1,9 +1,5 @@ -/* -pcilib_register_bank_description_t ipecamera_register_banks[] = { - { PCILIB_REGISTER_DMABANK0, PCILIB_BAR0, 128, PCILIB_DEFAULT_PROTOCOL, DMA_NWL_OFFSET, DMA_NWL_OFFSET, PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "%lx", "dma", "NorthWest Logick DMA Engine" }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL } -}; -*/ +#ifndef _PCILIB_NWL_REGISTERS_H +#define _PCILIB_NWL_REGISTERS_H // DMA static pcilib_register_description_t nwl_dma_registers[] = { @@ -92,3 +88,6 @@ static pcilib_register_description_t nwl_xrawdata_registers[] = { {0x910C, 0, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "xrawdata_data_mistmatch", ""}, {0, 0, 0, 0, 0x00000000, 0, 0, 0, NULL, NULL} }; + +int nwl_add_registers(nwl_dma_t *ctx); +#endif /* _PCILIB_NWL_REGISTERS_H */ |