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| author | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-14 06:01:27 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-14 06:01:27 +0200 |
| commit | f4ad2df2209acac66f3df47d847f1f714283feab (patch) | |
| tree | 23da0368acbb6c15cdebd2a35808cd6bbe99b8ae /dma/nwl_register.h | |
| parent | b492b1aac3d12683ccbc973b08b023ba0466cbec (diff) | |
| download | ipecamera-f4ad2df2209acac66f3df47d847f1f714283feab.tar.gz ipecamera-f4ad2df2209acac66f3df47d847f1f714283feab.tar.bz2 ipecamera-f4ad2df2209acac66f3df47d847f1f714283feab.tar.xz ipecamera-f4ad2df2209acac66f3df47d847f1f714283feab.zip | |
First iteration of work to preserve DMA state between executions
Diffstat (limited to 'dma/nwl_register.h')
| -rw-r--r-- | dma/nwl_register.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/dma/nwl_register.h b/dma/nwl_register.h index df479e9..926f093 100644 --- a/dma/nwl_register.h +++ b/dma/nwl_register.h @@ -56,8 +56,8 @@ static pcilib_register_description_t nwl_dma_engine_registers[] = { {0x0004, 4, 1, 0, 0x0000C100, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_descriptor_fetch_error", ""}, {0x0004, 5, 1, 0, 0x0000C100, PCILIB_REGISTER_RW1C, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_sw_abort_error", ""}, {0x0004, 8, 1, 0, 0x0000C100, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_enable", ""}, - {0x0004, 9, 1, 0, 0x0000C100, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_running", ""}, - {0x0004, 10, 1, 0, 0x0000C100, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_waiting", ""}, + {0x0004, 10, 1, 0, 0x0000C100, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_running", ""}, + {0x0004, 11, 1, 0, 0x0000C100, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_waiting", ""}, {0x0004, 14, 1, 0, 0x0000C100, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_reset_request", ""}, {0x0004, 15, 1, 0, 0x0000C100, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_reset", ""}, {0x0008, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma%0*u%s_next_descriptor", ""}, |