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| author | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-08 14:07:59 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-07-08 14:07:59 +0200 |
| commit | 80d999195b2b1896fcd1878a44b0ece474fe678c (patch) | |
| tree | 2b9d61aa800703c24557d3d39d9742a328668382 /dma | |
| parent | 5c1e2da736a77fc7172da2c621310a9ceaf1e6ce (diff) | |
| download | ipecamera-80d999195b2b1896fcd1878a44b0ece474fe678c.tar.gz ipecamera-80d999195b2b1896fcd1878a44b0ece474fe678c.tar.bz2 ipecamera-80d999195b2b1896fcd1878a44b0ece474fe678c.tar.xz ipecamera-80d999195b2b1896fcd1878a44b0ece474fe678c.zip | |
Add some check to verify if NWL DMA engine have been successfully initialized
Diffstat (limited to 'dma')
| -rw-r--r-- | dma/nwl.c | 8 |
1 files changed, 3 insertions, 5 deletions
@@ -26,13 +26,10 @@ pcilib_register_bank_description_t ipecamera_register_banks[] = { { PCILIB_REGISTER_DMABANK0, PCILIB_BAR0, 128, PCILIB_DEFAULT_PROTOCOL, DMA_NWL_OFFSET, DMA_NWL_OFFSET, PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "%lx", "dma", "NorthWest Logick DMA Engine" }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL } }; - -pcilib_register_description_t dma_nwl_registers[] = { - {0, 0, 32, 0, PCILIB_REGISTER_R , PCILIB_REGISTER_DMABANK, "dma_capabilities", ""}, - {1, 0, 32, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_DMABANK, "dma_control", ""}, -}; */ + + typedef struct { pcilib_dma_engine_description_t desc; char *base_addr; @@ -71,6 +68,7 @@ static int nwl_read_engine_config(nwl_dma_t *ctx, pcilib_nwl_engine_description_ if ((val & DMA_ENG_PRESENT_MASK) == 0) return PCILIB_ERROR_NOTAVAILABLE; info->desc.addr = (val & DMA_ENG_NUMBER) >> DMA_ENG_NUMBER_SHIFT; + if ((info->desc.addr > PCILIB_MAX_DMA_ENGINES)||(info->desc.addr < 0)) return PCILIB_ERROR_INVALID_DATA; switch (val & DMA_ENG_DIRECTION_MASK) { case DMA_ENG_C2S: |