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* Support writting output to fileSuren A. Chilingaryan2011-07-182-48/+73
* Change timeout definition in Events API from struct timespec to pcilib_timeout_tSuren A. Chilingaryan2011-07-186-18/+24
* Prevent driver holding hardware locks from unloadingSuren A. Chilingaryan2011-07-184-12/+59
* Provide few scripts to test DMASuren A. Chilingaryan2011-07-172-0/+43
* Correctly check if DMA is already enabledSuren A. Chilingaryan2011-07-171-1/+1
* Do not try to verify write-only registersSuren A. Chilingaryan2011-07-172-11/+16
* Support forceful clean-up of kernel memorySuren A. Chilingaryan2011-07-176-36/+126
* List kernel buffersSuren A. Chilingaryan2011-07-175-38/+205
* Few more fixesSuren A. Chilingaryan2011-07-173-8/+21
* Correctly detect the tail pointer of C2S ringSuren A. Chilingaryan2011-07-174-34/+19
* Stop only started enginesSuren A. Chilingaryan2011-07-171-3/+18
* Handle correctly reference counting in the driverSuren A. Chilingaryan2011-07-178-28/+52
* Few fixesSuren A. Chilingaryan2011-07-176-27/+53
* Implement DMA access synchronization for NWL implementationSuren A. Chilingaryan2011-07-1711-137/+311
* Implement DMA access synchronization in the driverSuren A. Chilingaryan2011-07-1613-76/+268
* Provide formal description of DMA access synchronizationSuren A. Chilingaryan2011-07-162-9/+155
* First iteration of work to preserve DMA state between executionsSuren A. Chilingaryan2011-07-1417-215/+347
* Support modifications of DMA engine and allow DMA customizations by Event engineSuren A. Chilingaryan2011-07-1412-96/+123
* Add timeout to pcilib_skip_dmaSuren A. Chilingaryan2011-07-141-4/+21
* Support iterations argument and fix interpretation of size argument for bench...Suren A. Chilingaryan2011-07-131-6/+14
* Report writted register in hex if it was specified in hexSuren A. Chilingaryan2011-07-121-3/+23
* Few fixesSuren A. Chilingaryan2011-07-124-14/+34
* Separate NWL loopback code, provide DMA start/stop interfacesSuren A. Chilingaryan2011-07-1211-82/+181
* Another reorganization of NWL sourcesSuren A. Chilingaryan2011-07-127-286/+302
* Provide IRQ enable/disable callSuren A. Chilingaryan2011-07-1210-30/+171
* Suppport DMA modes in console application (not functional yet)Suren A. Chilingaryan2011-07-1212-33/+233
* Few fixesSuren A. Chilingaryan2011-07-122-8/+25
* Fix compilation issuesSuren A. Chilingaryan2011-07-113-8/+8
* Reorganization of NWL engine, step 1Suren A. Chilingaryan2011-07-115-128/+176
* Wait for the completion of DMA operations during writesSuren A. Chilingaryan2011-07-119-349/+431
* Minor improvementSuren A. Chilingaryan2011-07-111-7/+7
* Change cli parameters (reserve -t parameter for future use as timeout)Suren A. Chilingaryan2011-07-111-25/+41
* IRQ support in NWL DMA engineSuren A. Chilingaryan2011-07-1118-206/+306
* Support dynamic registers, support register offsets and multiregisters (bitma...Suren A. Chilingaryan2011-07-0916-202/+468
* Add some check to verify if NWL DMA engine have been successfully initializedSuren A. Chilingaryan2011-07-081-5/+3
* Support alignments in kmem allocationSuren A. Chilingaryan2011-07-063-12/+21
* Fix segmentation failure in DMA access modeSuren A. Chilingaryan2011-07-061-1/+5
* Compilation fixSuren A. Chilingaryan2011-07-061-4/+4
* A bit of renamingSuren A. Chilingaryan2011-07-069-55/+51
* Include type in the register descriptionSuren A. Chilingaryan2011-07-063-60/+62
* Support FIFO reading/writting, code restructurization, few fixesSuren A. Chilingaryan2011-07-0611-571/+785
* Define addresses of NWL enginesroot2011-07-041-1/+3
* North West Logick DMA implementationroot2011-07-0422-227/+1367
* DMA engine initialization and basic intrastructure for DMA read/writeroot2011-06-185-27/+189
* Enumerate DMA enginesroot2011-06-179-25/+255
* New reset routineroot2011-06-161-3/+3
* A bit of DMA infrastructureroot2011-06-167-24/+126
* Remove unsupported devicesroot2011-06-164-83/+8
* Move to new FPGA designroot2011-06-168-82/+179
* 32 bit fixSuren A. Chilingaryan2011-06-071-1/+1
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