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| author | zilio nicolas <nicolas.zilio@kit.edu> | 2015-08-26 14:45:18 +0200 |
|---|---|---|
| committer | zilio nicolas <nicolas.zilio@kit.edu> | 2015-08-26 14:45:18 +0200 |
| commit | 1e5f0b6d5e02c0dc11bedefa92fc3c5bb406845a (patch) | |
| tree | a978bd11f64f619ee8f40e42e73a582754c122de /dma/ipe.h | |
| parent | 0f298bd861ac8d847f33d6b8bc73b089d2749bbb (diff) | |
| parent | 6bad94bb8546a3a5595d340e7a2d809635e3bd5d (diff) | |
| download | pcitool-1e5f0b6d5e02c0dc11bedefa92fc3c5bb406845a.tar.gz pcitool-1e5f0b6d5e02c0dc11bedefa92fc3c5bb406845a.tar.bz2 pcitool-1e5f0b6d5e02c0dc11bedefa92fc3c5bb406845a.tar.xz pcitool-1e5f0b6d5e02c0dc11bedefa92fc3c5bb406845a.zip | |
pull from server
Diffstat (limited to 'dma/ipe.h')
| -rw-r--r-- | dma/ipe.h | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -65,6 +65,9 @@ static const pcilib_register_description_t ipe_dma_registers[] = { {0x000C, 24, 8, 0, 0xFFFFFFFF, PCILIB_REGISTER_RW , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "mwr_up_addr", "Upper address for 64 bit memory addressing"}, {0x0010, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_count", "Write DMA TLP Count"}, {0x0014, 0, 32, 0, 0x00000000, PCILIB_REGISTER_RW , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_pattern", "DMA generator data pattern"}, + {0x0018, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "dma_mode_flags", "DMA operation mode"}, + {0x0018, 0, 4, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "pcie_gen", "PCIe version 2/3 depending on the used XILINX core"}, + {0x0018, 4, 1, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "streaming_dma", "Streaming mode (enabled/disabled)"}, {0x0028, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "mwr_perf", "MWR Performance"}, {0x003C, 0, 32, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK_DMA, "cfg_lnk_width", "Negotiated and max width of PCIe Link"}, {0x003C, 0, 6, 0, 0x00000000, PCILIB_REGISTER_R , PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK_DMA, "cfg_cap_max_lnk_width", "Max link width"}, |