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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-05-07 05:03:18 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-05-07 05:03:18 +0200 |
| commit | e202b682db9b5241c59de3d934d64205a3df091d (patch) | |
| tree | 503ad01b0e621b41fb00a96adf6f5192fcc1f550 /dma/ipe_private.h | |
| parent | de9a65e8c7d73974816d715c0485e2756848ae5f (diff) | |
| download | pcitool-e202b682db9b5241c59de3d934d64205a3df091d.tar.gz pcitool-e202b682db9b5241c59de3d934d64205a3df091d.tar.bz2 pcitool-e202b682db9b5241c59de3d934d64205a3df091d.tar.xz pcitool-e202b682db9b5241c59de3d934d64205a3df091d.zip | |
Dynamicly set TLP(Payload) size in IPEDMA
Diffstat (limited to 'dma/ipe_private.h')
| -rw-r--r-- | dma/ipe_private.h | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/dma/ipe_private.h b/dma/ipe_private.h index 1fb4e9e..ae5df1c 100644 --- a/dma/ipe_private.h +++ b/dma/ipe_private.h @@ -5,22 +5,25 @@ #define IPEDMA_64BIT_MODE 1 /**< 64-bit mode addressing is required to support PCIe gen3 */ #define IPEDMA_CORES 1 -#define IPEDMA_TLP_SIZE 32 +#define IPEDMA_MAX_TLP_SIZE 256 /**< Defines maximum TLP in bytes supported by device */ +//#define IPEDMA_TLP_SIZE 128 /**< If set, enforces the specified TLP size */ + #define IPEDMA_PAGE_SIZE 4096 #define IPEDMA_DMA_PAGES 32 /**< number of DMA pages in the ring buffer to allocate */ #define IPEDMA_DMA_PROGRESS_THRESHOLD 1 /**< how many pages the DMA engine should fill before reporting progress */ #define IPEDMA_DESCRIPTOR_SIZE 128 #define IPEDMA_DESCRIPTOR_ALIGNMENT 64 -#define IPEDMA_BUG_LAST_READ /**< We should forbid writting the second last available DMA buffer (the last is forbidden by design) */ -#define IPEDMA_RESET_DELAY 100000 /**< Sleep between accessing DMA control and reset registers */ -#define IPEDMA_ADD_PAGE_DELAY 1000 /**< Delay between submitting successive DMA pages into IPEDMA_REG_PAGE_ADDR register */ -#define IPEDMA_NODATA_SLEEP 10 /**< To keep CPU free */ //#define IPEDMA_BUG_DMARD /**< No register read during DMA transfer */ +//#define IPEDMA_BUG_LAST_READ /**< We should forbid writting the second last available DMA buffer (the last is forbidden by design) */ //#define IPEDMA_DETECT_PACKETS /**< Using empty_deceted flag */ #define IPEDMA_SUPPORT_EMPTY_DETECTED /**< Avoid waiting for data when empty_detected flag is set in hardware */ -#define IPEDMA_DMA_TIMEOUT 100000 /**< us, overrides PCILIB_DMA_TIMEOUT (actual hardware timeout is 50ms according to Lorenzo) */ + +#define IPEDMA_DMA_TIMEOUT 100000 /**< us, overrides PCILIB_DMA_TIMEOUT (actual hardware timeout is 50ms according to Lorenzo) */ +#define IPEDMA_RESET_DELAY 100000 /**< Sleep between accessing DMA control and reset registers */ +#define IPEDMA_ADD_PAGE_DELAY 1000 /**< Delay between submitting successive DMA pages into IPEDMA_REG_PAGE_ADDR register */ +#define IPEDMA_NODATA_SLEEP 10 /**< To keep CPU free */ #define IPEDMA_REG_RESET 0x00 #define IPEDMA_REG_CONTROL 0x04 |