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| author | Suren A. Chilingaryan <csa@suren.me> | 2015-04-27 01:54:44 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2015-04-27 01:54:44 +0200 |
| commit | 8d3ad26d8331c43659d0d4e77e8a50fbc3cfc1e4 (patch) | |
| tree | 30c74c76115279cdc15437a07fabd8347ac1fdfd /dma/nwl_engine.c | |
| parent | dcd8ad63316eac672492bc18112bbbb52811c3fc (diff) | |
| download | pcitool-8d3ad26d8331c43659d0d4e77e8a50fbc3cfc1e4.tar.gz pcitool-8d3ad26d8331c43659d0d4e77e8a50fbc3cfc1e4.tar.bz2 pcitool-8d3ad26d8331c43659d0d4e77e8a50fbc3cfc1e4.tar.xz pcitool-8d3ad26d8331c43659d0d4e77e8a50fbc3cfc1e4.zip | |
Further adjustments to get ready for independent event plugins
Diffstat (limited to 'dma/nwl_engine.c')
| -rw-r--r-- | dma/nwl_engine.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/dma/nwl_engine.c b/dma/nwl_engine.c index a437948..6930533 100644 --- a/dma/nwl_engine.c +++ b/dma/nwl_engine.c @@ -93,7 +93,7 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { do { nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); gettimeofday(&cur, NULL); - } while ((val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT)); + } while ((val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_NWL_REGISTER_TIMEOUT)); if (val & (DMA_ENG_STATE_MASK|DMA_ENG_USER_RESET)) { pcilib_error("Timeout during reset of DMA engine %i", ectx->desc->addr); @@ -110,7 +110,7 @@ int dma_nwl_start_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { do { nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); gettimeofday(&cur, NULL); - } while ((val & DMA_ENG_RESET)&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT)); + } while ((val & DMA_ENG_RESET)&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_NWL_REGISTER_TIMEOUT)); if (val & DMA_ENG_RESET) { pcilib_error("Timeout during reset of DMA engine %i", ectx->desc->addr); @@ -183,7 +183,7 @@ int dma_nwl_stop_engine(nwl_dma_t *ctx, pcilib_dma_engine_t dma) { do { nwl_read_register(val, ctx, base, REG_DMA_ENG_CTRL_STATUS); gettimeofday(&cur, NULL); - } while ((val & (DMA_ENG_RUNNING))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_REGISTER_TIMEOUT)); + } while ((val & (DMA_ENG_RUNNING))&&(((cur.tv_sec - start.tv_sec)*1000000 + (cur.tv_usec - start.tv_usec)) < PCILIB_NWL_REGISTER_TIMEOUT)); if (ectx->ring) { ring_pa = pcilib_kmem_get_pa(ctx->dmactx.pcilib, ectx->ring); |