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authorVasilii Chernov <vchernov@inr.ru>2016-02-24 18:24:22 +0100
committerVasilii Chernov <vchernov@inr.ru>2016-02-24 18:24:22 +0100
commitb0a034e6ef4a958235a56ebde0831c0f30a84d30 (patch)
treea1f46d2d536c692edd6b17efc61ac9fefef2796b /docs/ToDo
parentda842568b94b0e00c1709ae01f441a7424c15b87 (diff)
parent3ea1907f3169e0233d3a32a7d470af3c34b6f967 (diff)
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Merge with Suren branch. Fix memory leaks.
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1 files changed, 7 insertions, 6 deletions
diff --git a/docs/ToDo b/docs/ToDo
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@@ -11,12 +11,11 @@ High Priority (we would need it for IPE Camera)
Normal Priority (it would make just few things a bit easier)
===============
- 1. Support Python-scripts in the views (we need to provide python API to read registers/properties)
- 2. Integrate base streaming model into the pcitool
- 3. Implement pcilib_configure_autotrigger
- 4. Really check the specified min, max values while setting registers
- 5. Provide OR and AND operations on registers in cli
- 6. Support writting a data from a binary file in cli
+ 1. Integrate base streaming model into the pcitool
+ 2. Implement pcilib_configure_autotrigger
+ 3. Really check the specified min, max values while setting registers
+ 4. Provide OR and AND operations on registers in cli
+ 5. Support writting a data from a binary file in cli
Low Priority (only as generalization for other projects)
============
@@ -25,6 +24,8 @@ Low Priority (only as generalization for other projects)
3. Define a syntax for register dependencies / delays (?)
4. Use pthread_condition_t instead of polling
5. Support FIFO reads/writes from/to registers
+ 6. OPC UA interface to the registers
+ 7. Generate XML models from SystemRDL descriptions
Performance
===========