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authorSuren A. Chilingaryan <csa@dside.dyndns.org>2011-10-21 03:44:27 +0200
committerSuren A. Chilingaryan <csa@dside.dyndns.org>2011-10-21 03:44:27 +0200
commit32bd82e4b4748cbe7b4734030dfb135feab4dffc (patch)
tree5a4a6c77d2f51f4d8e9081961b31bb6b53c64948 /ipecamera/model.h
parentb407c19d68509af786ed13fb22e66bebbf73c0d8 (diff)
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Accept short addresses for IPECamera FPGA registers
Diffstat (limited to 'ipecamera/model.h')
-rw-r--r--ipecamera/model.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/ipecamera/model.h b/ipecamera/model.h
index 2dec30a..91f68ed 100644
--- a/ipecamera/model.h
+++ b/ipecamera/model.h
@@ -72,7 +72,7 @@ pcilib_register_description_t ipecamera_registers[] = {
{112, 0, 2, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "adc_resolution", ""},
{115, 0, 1, 1, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "special_115", ""},
/*{126, 0, 16, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK0, "temp", ""},*/
-{0, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
+{0x00, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
{0x10, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
{0x20, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
{0x30, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_version", ""},
@@ -88,7 +88,9 @@ pcilib_register_description_t ipecamera_registers[] = {
};
pcilib_register_range_t ipecamera_register_ranges[] = {
- {0, 128, PCILIB_REGISTER_BANK0}, {0, 0, 0}
+ {0, 128, PCILIB_REGISTER_BANK0, 0},
+ {0x9000, 0x9FFF, PCILIB_REGISTER_BANK1, -0x9000},
+ {0, 0, 0, 0}
};
pcilib_event_description_t ipecamera_events[] = {