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| author | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-04-13 20:02:27 +0200 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@dside.dyndns.org> | 2011-04-13 20:02:27 +0200 |
| commit | e1fe3e593f849595ac5843b3773710091a6958cb (patch) | |
| tree | 602ed23cbc51e2044f4113c46aaa046ada5f7ace /ipecamera/model.h | |
| parent | b5eac3af41cb8c752b6779dd36c314f8f6caeccf (diff) | |
| download | pcitool-e1fe3e593f849595ac5843b3773710091a6958cb.tar.gz pcitool-e1fe3e593f849595ac5843b3773710091a6958cb.tar.bz2 pcitool-e1fe3e593f849595ac5843b3773710091a6958cb.tar.xz pcitool-e1fe3e593f849595ac5843b3773710091a6958cb.zip | |
Add special CMOSIS registers
Diffstat (limited to 'ipecamera/model.h')
| -rw-r--r-- | ipecamera/model.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/ipecamera/model.h b/ipecamera/model.h index 422092b..07f405a 100644 --- a/ipecamera/model.h +++ b/ipecamera/model.h @@ -54,6 +54,7 @@ pcilib_register_description_t ipecamera_registers[] = { {72, 0, 2, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "output_mode", ""}, {78, 0, 12, 85, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "training_pattern", ""}, {80, 0, 18, 0x3FFFF,PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "channel_en", ""}, +{82, 0, 3, 7, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "special_82", ""}, {89, 0, 8, 96, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "vlow2", ""}, {90, 0, 8, 96, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "vlow3", ""}, {100, 0, 14, 16260, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "offset", ""}, @@ -61,6 +62,7 @@ pcilib_register_description_t ipecamera_registers[] = { {103, 0, 8, 32, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "adc_gain", ""}, {111, 0, 1, 1, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "bit_mode", ""}, {112, 0, 2, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "adc_resolution", ""}, +{115, 0, 1, 1, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "special_115", ""}, /*{126, 0, 16, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "temp", ""},*/ {0, 0, 32, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "spi_conf_input", ""}, {1, 0, 32, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BANK1, "spi_conf_output", ""}, |