Move to new FPGA design

3 files changed, 29 insertions, 23 deletions

diff --git a/ipecamera/image.c b/ipecamera/image.c
index 9718e85..4d55069 100644
--- a/ipecamera/image.c
+++ b/ipecamera/image.c
@@ -136,12 +136,13 @@ pcilib_context_t *ipecamera_init(pcilib_t *pcilib) {
 
 	ctx->buffer_size = IPECAMERA_DEFAULT_BUFFER_SIZE;
 	ctx->dim.bpp = sizeof(ipecamera_pixel_t) * 8;
-
+/*
 	ctx->data = pcilib_resolve_data_space(pcilib, 0, &ctx->size);
 	if (!ctx->data) {
 	    err = -1;
 	    pcilib_error("Unable to resolve the data space");
 	}
+*/
 	
 	FIND_REG(status_reg, "fpga", "status");
 	FIND_REG(control_reg, "fpga", "control");
@@ -240,8 +241,10 @@ int ipecamera_reset(pcilib_context_t *vctx) {
     if (err) return err;
     
 	// This is temporary for verification purposes
-    memset(ctx->data, 0, ctx->size);
+    if (ctx->data) memset(ctx->data, 0, ctx->size);
 
+    usleep(10000);
+    
     err = pcilib_read_register_by_id(pcilib, status, &value);
     if (err) {
 	pcilib_error("Error reading status register");
@@ -249,7 +252,7 @@ int ipecamera_reset(pcilib_context_t *vctx) {
     }
 
     if (value != IPECAMERA_EXPECTED_STATUS) {
-	pcilib_error("Unexpected value (%lx) of status register", value);
+	pcilib_error("Unexpected value (%lx) of status register, expected %lx", value, IPECAMERA_EXPECTED_STATUS);
 	return PCILIB_ERROR_VERIFY;
     }
 
@@ -477,6 +480,8 @@ static int ipecamera_get_image(ipecamera_t *ctx) {
     ipecamera_payload_t *linebuf = (ipecamera_payload_t*)malloc(max_size * sizeof(ipecamera_payload_t));
     if (!linebuf) return PCILIB_ERROR_MEMORY;
 
+    if (!ctx->data) return PCILIB_ERROR_NOTSUPPORTED;
+    
 #ifdef IPECAMERA_WRITE_RAW
     FILE *f = fopen("raw/image.raw", "w");
     if (f) fclose(f);
diff --git a/ipecamera/model.c b/ipecamera/model.c
index c258a32..23715e3 100644
--- a/ipecamera/model.c
+++ b/ipecamera/model.c
@@ -31,8 +31,8 @@ int ipecamera_read(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pcil
 
     assert(addr < 128);
     
-    wr =  pcilib_resolve_register_address(ctx, bank->write_addr);
-    rd =  pcilib_resolve_register_address(ctx, bank->read_addr);
+    wr =  pcilib_resolve_register_address(ctx, bank->bar, bank->write_addr);
+    rd =  pcilib_resolve_register_address(ctx, bank->bar, bank->read_addr);
     if ((!rd)||(!wr)) {
 	pcilib_error("Error resolving addresses of read & write registers");
 	return PCILIB_ERROR_INVALID_ADDRESS;
@@ -121,8 +121,8 @@ int ipecamera_write(pcilib_t *ctx, pcilib_register_bank_description_t *bank, pci
     assert(addr < 128);
     assert(value < 256);
     
-    wr =  pcilib_resolve_register_address(ctx, bank->write_addr);
-    rd =  pcilib_resolve_register_address(ctx, bank->read_addr);
+    wr =  pcilib_resolve_register_address(ctx, bank->bar, bank->write_addr);
+    rd =  pcilib_resolve_register_address(ctx, bank->bar, bank->read_addr);
     if ((!rd)||(!wr)) {
 	pcilib_error("Error resolving addresses of read & write registers");
 	return PCILIB_ERROR_INVALID_ADDRESS;
diff --git a/ipecamera/model.h b/ipecamera/model.h
index c3d82e3..9898084 100644
--- a/ipecamera/model.h
+++ b/ipecamera/model.h
@@ -6,15 +6,16 @@
 #include "pcilib.h"
 #include "image.h"
 
-#define IPECAMERA_REGISTER_SPACE 0xfeaffc00
+//#define IPECAMERA_REGISTER_SPACE 0xfeaffc00
+#define IPECAMERA_REGISTER_SPACE 0x9000
 #define IPECAMERA_REGISTER_WRITE (IPECAMERA_REGISTER_SPACE + 0)
-#define IPECAMERA_REGISTER_READ (IPECAMERA_REGISTER_WRITE + 4)
+#define IPECAMERA_REGISTER_READ (IPECAMERA_REGISTER_WRITE + 16)
 
 #ifdef _IPECAMERA_MODEL_C
 pcilib_register_bank_description_t ipecamera_register_banks[] = {
-    { PCILIB_REGISTER_BANK0, 128, IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ,	IPECAMERA_REGISTER_WRITE, PCILIB_BIG_ENDIAN, 8, PCILIB_LITTLE_ENDIAN, "cmosis", "CMOSIS CMV2000 Registers" },
-    { PCILIB_REGISTER_BANK1, 64, PCILIB_DEFAULT_PROTOCOL, IPECAMERA_REGISTER_SPACE, IPECAMERA_REGISTER_SPACE, PCILIB_BIG_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "fpga", "IPECamera Registers" },
-    { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL }
+    { PCILIB_REGISTER_BANK0, PCILIB_BAR0, 128, IPECAMERA_REGISTER_PROTOCOL, IPECAMERA_REGISTER_READ, IPECAMERA_REGISTER_WRITE, PCILIB_LITTLE_ENDIAN, 8, PCILIB_LITTLE_ENDIAN, "%lu", "cmosis", "CMOSIS CMV2000 Registers" },
+    { PCILIB_REGISTER_BANK1, PCILIB_BAR0,  64, PCILIB_DEFAULT_PROTOCOL, IPECAMERA_REGISTER_SPACE, IPECAMERA_REGISTER_SPACE, PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "0x%lx", "fpga", "IPECamera Registers" },
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
 };
 
 pcilib_register_description_t ipecamera_registers[] = {
@@ -65,17 +66,17 @@ pcilib_register_description_t ipecamera_registers[] = {
 {115, 	0, 	1, 	1, 	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "special_115", ""},
 /*{126, 	0, 	16, 	0, 	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK0, "temp", ""},*/
 {0,	0, 	32,	0,	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
-{1,	0, 	32,	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
-{2,	0, 	32,	0,	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
-{3,	0, 	32,	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "firmware_version", ""},
-{4,	0, 	32, 	0,	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "control", ""},
-{5,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "status", ""},
-{6,	0, 	16,	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "cmosis_temperature", ""},
-{7,	0, 	32,	0,	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "temperature_sample_timing", ""},
-{8,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "start_address", ""},
-{9,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "end_address", ""},
-{10,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "last_write_address", ""},
-{11,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "last_write_value", ""},
+{4,	0, 	32,	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
+{8,	0, 	32,	0,	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
+{12,	0, 	32,	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "firmware_version", ""},
+{16,	0, 	32, 	0,	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "control", ""},
+{20,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "status", ""},
+{24,	0, 	16,	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "cmosis_temperature", ""},
+{28,	0, 	32,	0,	PCILIB_REGISTER_RW, PCILIB_REGISTER_BANK1, "temperature_sample_timing", ""},
+{32,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "start_address", ""},
+{36,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "end_address", ""},
+{40,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "last_write_address", ""},
+{44,	0, 	32, 	0,	PCILIB_REGISTER_R,  PCILIB_REGISTER_BANK1, "last_write_value", ""},
 {0,	0,	0,	0,	0,                  0,                     NULL, NULL}
 };