registers and banks support in xml v1. pci -ll works fine, but got segfault on pci -r name and pci -r name gives 0 always. might be due to the order in pci.c ------> ask suren

4 files changed, 1188 insertions, 1 deletions

diff --git a/pcitool/camera.xml b/pcitool/camera.xml
new file mode 100644
index 0000000..753c707
--- /dev/null
+++ b/pcitool/camera.xml
@@ -0,0 +1,923 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+<model xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <banks>
+    <bank>
+     <bank_description>
+        <adress>bank 0</adress>
+        <bar>0</bar>
+        <size>128</size>
+        <protocol>default</protocol>
+        <read_adress>0x9010</read_adress>
+        <write_adress>0x9000</write_adress>
+        <word_size>8</word_size>
+        <endianess>little</endianess>
+        <format>%lu</format>
+        <name>cmosis</name>
+        <description>CMOSIS CMV2000 Registers</description>
+      </bank_description>
+      <registers>
+        <register>
+          <adress>1</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>1088</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines</name>
+	  <description>test</description>
+        </register>
+        <register>
+          <adress>3</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start1</name>
+        </register>
+        <register>
+          <adress>5</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start2</name>
+        </register>
+        <register>
+          <adress>7</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start3</name>
+        </register>
+        <register>
+          <adress>9</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start4</name>
+        </register>
+        <register>
+          <adress>11</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start5</name>
+        </register>
+        <register>
+          <adress>13</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start6</name>
+        </register>
+        <register>
+          <adress>15</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start7</name>
+        </register>
+        <register>
+          <adress>17</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_start8</name>
+        </register>
+        <register>
+          <adress>19</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines1</name>
+        </register>
+        <register>
+          <adress>21</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines2</name>
+        </register>
+        <register>
+          <adress>23</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines3</name>
+        </register>
+        <register>
+          <adress>25</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines4</name>
+        </register>
+        <register>
+          <adress>27</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines5</name>
+        </register>
+        <register>
+          <adress>29</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines6</name>
+        </register>
+        <register>
+          <adress>31</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines7</name>
+        </register>
+        <register>
+          <adress>33</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_lines8</name>
+        </register>
+        <register>
+          <adress>35</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_sub_s</name>
+        </register>
+        <register>
+          <adress>37</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_sub_a</name>
+        </register>
+        <register>
+          <adress>39</adress>
+          <offset>0</offset>
+          <size>1</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_color</name>
+        </register>
+        <register>
+          <adress>40</adress>
+          <offset>0</offset>
+          <size>2</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_image_flipping</name>
+        </register>
+        <register>
+          <adress>41</adress>
+          <offset>0</offset>
+          <size>2</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_flags</name>
+        </register>
+        <register>
+          <adress>42</adress>
+          <offset>0</offset>
+          <size>24</size>
+          <default>1088</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_time</name>
+          <views>
+            <view>formuu3</view>
+            <view>enumm3</view>
+          </views>
+        </register>
+        <register>
+          <adress>45</adress>
+          <offset>0</offset>
+          <size>24</size>
+          <default>1088</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_step</name>
+        </register>
+        <register>
+          <adress>48</adress>
+          <offset>0</offset>
+          <size>24</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_kp1</name>
+        </register>
+        <register>
+          <adress>51</adress>
+          <offset>0</offset>
+          <size>24</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_kp2</name>
+        </register>
+        <register>
+          <adress>54</adress>
+          <offset>0</offset>
+          <size>2</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_nr_slopes</name>
+        </register>
+        <register>
+          <adress>55</adress>
+          <offset>0</offset>
+          <size>8</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_seq</name>
+        </register>
+        <register>
+          <adress>56</adress>
+          <offset>0</offset>
+          <size>24</size>
+          <default>1088</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_time2</name>
+        </register>
+        <register>
+          <adress>59</adress>
+          <offset>0</offset>
+          <size>24</size>
+          <default>1088</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_step2</name>
+        </register>
+        <register>
+          <adress>68</adress>
+          <offset>0</offset>
+          <size>2</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_nr_slopes2</name>
+        </register>
+        <register>
+          <adress>69</adress>
+          <offset>0</offset>
+          <size>8</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_exp_seq2</name>
+        </register>
+        <register>
+          <adress>70</adress>
+          <offset>0</offset>
+          <size>16</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_number_frames</name>
+        </register>
+        <register>
+          <adress>72</adress>
+          <offset>0</offset>
+          <size>2</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_output_mode</name>
+        </register>
+        <register>
+          <adress>78</adress>
+          <offset>0</offset>
+          <size>12</size>
+          <default>85</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_training_pattern</name>
+        </register>
+        <register>
+          <adress>80</adress>
+          <offset>0</offset>
+          <size>18</size>
+          <default>0x3FFFF</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_channel_en</name>
+        </register>
+        <register>
+          <adress>82</adress>
+          <offset>0</offset>
+          <size>3</size>
+          <default>7</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_special_82</name>
+        </register>
+        <register>
+          <adress>89</adress>
+          <offset>0</offset>
+          <size>8</size>
+          <default>96</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_vlow2</name>
+        </register>
+        <register>
+          <adress>90</adress>
+          <offset>0</offset>
+          <size>8</size>
+          <default>96</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_vlow3</name>
+        </register>
+        <register>
+          <adress>100</adress>
+          <offset>0</offset>
+          <size>14</size>
+          <default>16260</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_offset</name>
+        </register>
+        <register>
+          <adress>102</adress>
+          <offset>0</offset>
+          <size>2</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_pga</name>
+        </register>
+        <register>
+          <adress>103</adress>
+          <offset>0</offset>
+          <size>8</size>
+          <default>32</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_adc_gain</name>
+        </register>
+        <register>
+          <adress>111</adress>
+          <offset>0</offset>
+          <size>1</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_bit_mode</name>
+        </register>
+        <register>
+          <adress>112</adress>
+          <offset>0</offset>
+          <size>2</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_adc_resolution</name>
+        </register>
+        <register>
+          <adress>115</adress>
+          <offset>0</offset>
+          <size>1</size>
+          <default>1</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>cmosis_special_115</name>
+        </register>
+      </registers>
+    </bank>
+    <bank>
+      <bank_description>
+        <adress>bank 1</adress>
+        <bar>0</bar>
+        <size>0x0200</size>
+        <protocol>default</protocol>
+        <read_adress>0x9000</read_adress>
+        <write_adress>0x9000</write_adress>
+        <word_size>32</word_size>
+        <endianess>little</endianess>
+        <format>0x%lx</format>
+        <name>fpga</name>
+        <description>IPECamera Registers</description>
+      </bank_description>
+      <registers>
+        <register>
+          <adress>0x00</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>spi_conf_input</name>
+        </register>
+        <register>
+          <adress>0x10</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>spi_conf_output</name>
+        </register>
+        <register>
+          <adress>0x20</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>spi_clk_speed</name>
+        </register>
+        <register>
+          <adress>0x30</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>firmware_info</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>8</size>
+              <mode>R</mode>
+              <name>firmware_version</name>
+            </register_bits>
+            <register_bits>
+              <offset>8</offset>
+              <size>1</size>
+              <mode>R</mode>
+              <name>firmware_bitmode</name>
+            </register_bits>
+            <register_bits>
+              <offset>12</offset>
+              <size>2</size>
+              <mode>R</mode>
+              <name>adc_resolution</name>
+            </register_bits>
+            <register_bits>
+              <offset>16</offset>
+              <size>2</size>
+              <mode>R</mode>
+              <name>output_mode</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <adress>0x40</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>control</name>
+		<registers_bits>
+        	    <register_bits>
+              		<offset>31</offset>
+	                <size>1</size>
+	                <mode>R</mode>
+          	        <name>freq</name>
+            	    </register_bits>
+		</registers_bits>	
+        </register>
+        <register>
+          <adress>0x50</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>status</name>
+        </register>
+        <register>
+          <adress>0x54</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>status2</name>
+        </register>
+        <register>
+          <adress>0x58</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>status3</name>
+        </register>
+        <register>
+          <adress>0x5c</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>fr_status</name>
+        </register>
+        <register>
+          <adress>0x70</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>start_address</name>
+        </register>
+        <register>
+          <adress>0x74</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>end_address</name>
+        </register>
+        <register>
+          <adress>0x78</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>rd_address</name>
+        </register>
+        <register>
+          <adress>0xa0</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>fr_param1</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>10</size>
+              <mode>RW</mode>
+              <name>fr_skip_lines</name>
+            </register_bits>
+            <register_bits>
+              <offset>10</offset>
+              <size>11</size>
+              <mode>RW</mode>
+              <name>fr_num_lines</name>
+            </register_bits>
+            <register_bits>
+              <offset>21</offset>
+              <size>11</size>
+              <mode>RW</mode>
+              <name>fr_start_address</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <adress>0xb0</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>all bits</rwmask>
+          <mode>RW</mode>
+          <name>fr_param2</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>11</size>
+              <mode>RW</mode>
+              <name>fr_threshold_start_line</name>
+            </register_bits>
+            <register_bits>
+              <offset>16</offset>
+              <size>10</size>
+              <mode>RW</mode>
+              <name>fr_area_lines</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <adress>0xc0</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>skiped_lines</name>
+        </register>
+        <register>
+          <adress>0xd0</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>all bits</rwmask>
+          <mode>RW</mode>
+          <name>fr_thresholds</name>
+        </register>
+        <register>
+          <adress>0xd0</adress>
+          <offset>0</offset>
+          <size>10</size>
+          <default>0</default>
+          <rwmask>all bits</rwmask>
+          <mode>RW</mode>
+          <name>fr_pixel_thr</name>
+        </register>
+        <register>
+          <adress>0xd0</adress>
+          <offset>10</offset>
+          <size>11</size>
+          <default>0</default>
+          <rwmask>all bits</rwmask>
+          <mode>RW</mode>
+          <name>fr_num_pixel_thr</name>
+        </register>
+        <register>
+          <adress>0xd0</adress>
+          <offset>21</offset>
+          <size>11</size>
+          <default>0</default>
+          <rwmask>all bits</rwmask>
+          <mode>RW</mode>
+          <name>fr_num_lines_thr</name>
+        </register>
+        <register>
+          <adress>0x100</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>rawdata_pkt_addr</name>
+        </register>
+        <register>
+          <adress>0x110</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>temperature_info</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>16</size>
+              <mode>R</mode>
+              <name>sensor_temperature</name>
+		<views>
+		<view>formuu1</view>
+		<view>formuu2</view>
+                <view>enumm2</view>
+              </views>
+            </register_bits>
+            <register_bits>
+              <offset>16</offset>
+              <size>3</size>
+              <mode>R</mode>
+              <name>sensor_temperature_alarms</name>
+            </register_bits>
+            <register_bits>
+              <offset>19</offset>
+              <size>10</size>
+              <mode>RW</mode>
+              <name>fpga_temperature</name>
+              <views>
+                <view>formuu1</view>
+                <view>enumm1</view>
+              </views>
+            </register_bits>
+            <register_bits>
+              <offset>29</offset>
+              <size>3</size>
+              <mode>R</mode>
+              <name>fpga_temperature_alarms</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <adress>0x120</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>num_lines</name>
+        </register>
+        <register>
+          <adress>0x130</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>start_line</name>
+        </register>
+        <register>
+          <adress>0x140</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>exp_time</name>
+        </register>
+        <register>
+          <adress>0x150</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>motor</name>
+          <registers_bits>
+            <register_bits>
+              <offset>0</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_phi</name>
+            </register_bits>
+            <register_bits>
+              <offset>5</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_z</name>
+            </register_bits>
+            <register_bits>
+              <offset>10</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_y</name>
+            </register_bits>
+            <register_bits>
+              <offset>15</offset>
+              <size>5</size>
+              <mode>RW</mode>
+              <name>motor_x</name>
+            </register_bits>
+            <register_bits>
+              <offset>20</offset>
+              <size>8</size>
+              <mode>R</mode>
+              <name>adc_gain</name>
+            </register_bits>
+          </registers_bits>
+        </register>
+        <register>
+          <adress>0x160</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>write_status</name>
+        </register>
+        <register>
+          <adress>0x170</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>num_triggers</name>
+        </register>
+        <register>
+          <adress>0x180</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0x280</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>trigger_period</name>
+	  <views>
+		<view>enumm2</view>
+	  </views>
+        </register>
+        <register>
+          <adress>0x190</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>temperature_sample_period</name>
+        </register>
+        <register>
+          <adress>0x1a0</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0x64</default>
+          <rwmask>0</rwmask>
+          <mode>RW</mode>
+          <name>ddr_max_frames</name>
+        </register>
+        <register>
+          <adress>0x1b0</adress>
+          <offset>0</offset>
+          <size>32</size>
+          <default>0</default>
+          <rwmask>0</rwmask>
+          <mode>R</mode>
+          <name>ddr_num_frames</name>
+        </register>
+      </registers>
+    </bank>
+    <bank>
+	<bank_description>
+      <adress>DMA bank</adress>
+        <bar>0</bar>
+        <size>0x0200</size>
+        <protocol>default</protocol>
+        <read_adress>0x0</read_adress>
+        <write_adress>0x0</write_adress>
+        <word_size>32</word_size>
+        <endianess>little</endianess>
+        <format>0x%lx</format>
+        <name>dma</name>
+        <description>DMA Registers</description>
+	</bank_description>
+    </bank>
+  </banks>
+  <views>
+    <view type="formula">
+      <name>formuu1</name>
+	<unit>C</unit>
+      <read_from_register>(503975./1024000)*@reg - 27315./100</read_from_register>
+      <write_to_register>(@value + 27315./100)*(102400./503975)</write_to_register>
+<description>formula to get real fpga temperature from the fpga_temperature register in decimal</description>
+    </view>
+    <view type="enum">
+      <name>enumm1</name>
+      <enum value="0x100" min="0x2" max="0x300">high</enum>
+      <enum value="0x010">low</enum>
+	<description>enum towards temperatures register</description>
+    </view>
+    <view type="formula">
+      <name>formuu2</name>
+	<unit>C</unit>
+      <read_from_register>((1./4)*(@reg - 1200)) if @freq==0 else ((3./10)*(@reg - 1000))</read_from_register>
+      <write_to_register>4*@value + 1200 if @freq==0 else (10./3)*@value + 1000</write_to_register>
+      <description>formula to get real sensor temperature from the sensor_temperature register in decimal</description>
+    </view>
+    <view type="enum">
+      <name>enumm2</name>
+      <enum value="0x120">high</enum>
+      <enum value="0x010" min="0x00" max="0x020">low</enum>
+	   <description>enum towards sensor_temperature register</description>
+    </view>
+    <view type="formula">
+      <name>formuu3</name>
+	<unit>us</unit>  
+      <read_from_register>(@reg+(43./100))*129./(40*1000000)if @freq==0 else (@reg+(43./100))*129./(48*1000000)</read_from_register>
+      <write_to_register>@value/129.*(40*1000000) - 43./100 if @freq==0 else @value/129.*(48*1000000) - 43./100</write_to_register>
+	<description>formula to get real exposure time from the cmosis_exp_time register in decimal</description> 
+    </view>
+    <view type="enum">
+      <name>enumm3</name>
+      <enum  value="0x000">short</enum>
+      <enum  value="0x010">mid</enum>
+      <enum  value="0x100" min="0x0F0">long</enum>
+	<description>enum towards cmosis_exp_register register</description>
+    </view>
+  </views>
+</model>
diff --git a/pcitool/cli.c b/pcitool/cli.c
index 9eeb046..f105349 100644
--- a/pcitool/cli.c
+++ b/pcitool/cli.c
@@ -37,6 +37,7 @@
 #include "error.h"
 #include "debug.h"
 #include "model.h"
+#include "xml.h"
 
 /* defines */
 #define MAX_KBUF 14
@@ -89,7 +90,8 @@ typedef enum {
     MODE_ALLOC_KMEM,
     MODE_LIST_KMEM,
     MODE_READ_KMEM,
-    MODE_FREE_KMEM
+    MODE_FREE_KMEM,
+	MODE_VALIDATE_XML
 } MODE;
 
 typedef enum {
@@ -135,6 +137,7 @@ typedef enum {
     OPT_GRAB = 'g',
     OPT_QUIETE = 'q',
     OPT_HELP = 'h',
+	OPT_VALIDATE_XML= 'v',
     OPT_RESET = 128,
     OPT_BENCHMARK,
     OPT_TRIGGER,
@@ -182,6 +185,7 @@ static struct option long_options[] = {
     {"iterations",		required_argument, 0, OPT_ITERATIONS },
     {"info",			no_argument, 0, OPT_INFO },
     {"list",			no_argument, 0, OPT_LIST },
+	{"validate",		no_argument,0,OPT_VALIDATE_XML},
     {"reset",			no_argument, 0, OPT_RESET },
     {"benchmark",		optional_argument, 0, OPT_BENCHMARK },
     {"read",			optional_argument, 0, OPT_READ },
@@ -328,6 +332,8 @@ void Usage(int argc, char *argv[], const char *format, ...) {
 "	Data can be specified as sequence of hexdecimal number or\n"
 "	a single value prefixed with '*'. In this case it will be\n"
 "	replicated the specified amount of times\n"
+"  XML:\n"
+"  -v		-validates the xml file against xsd"	
 "\n\n",
 argv[0]);
 
@@ -3122,6 +3128,9 @@ int main(int argc, char **argv) {
 
 	// Requesting real-time priority when needed
     switch (mode) {
+	case MODE_VALIDATE_XML:
+	 	validation();
+	break;
      case MODE_READ:
      case MODE_WRITE:
         if (amode != ACCESS_DMA)
diff --git a/pcitool/config.txt b/pcitool/config.txt
new file mode 100644
index 0000000..14bcc57
--- /dev/null
+++ b/pcitool/config.txt
@@ -0,0 +1,13 @@
+///configuration///
+
+pwd to xml model file:
+camera.xml
+
+///pwd to units xml file:
+///units.xml
+///
+///pwd to python eval file:
+///pythonscripts.py
+///
+pwd to xsd schema file:
+registers_and_banks.xsd
diff --git a/pcitool/registers_and_banks.xsd b/pcitool/registers_and_banks.xsd
new file mode 100755
index 0000000..10d49b7
--- /dev/null
+++ b/pcitool/registers_and_banks.xsd
@@ -0,0 +1,242 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+<xsd:schema xmlns:xsd="http://www.w3.org/2001/XMLSchema">
+    
+    <xsd:element name="model">
+        <xsd:complexType>
+            <xsd:sequence>
+                <xsd:element name="banks" type="banks_type"/>
+                <xsd:element name="views" type="views_type" minOccurs="0" maxOccurs="1"/>
+            </xsd:sequence>
+        </xsd:complexType>
+        <xsd:key name="Registerkey">
+            <xsd:selector xpath="views/view/name"/>
+            <xsd:field xpath="."/>
+        </xsd:key>
+        <xsd:keyref refer="Registerkey" name="RegisterkeyRef">
+            <xsd:selector xpath="banks/bank/registers/register/views/view"/>
+            <xsd:field xpath="."/>
+        </xsd:keyref>
+        <xsd:key name="Registerbitskey">
+            <xsd:selector xpath="views/view/name"/>
+            <xsd:field xpath="."/>
+        </xsd:key>
+        <xsd:keyref refer="Registerbitskey" name="RegisterbitskeyRef">
+            <xsd:selector xpath="banks/bank/registers/register/registers_bits/register_bits/views/view"/>
+            <xsd:field xpath="."/>
+        </xsd:keyref>
+    </xsd:element>
+    
+    
+        <xsd:complexType name="views_type">
+            <xsd:sequence>
+                <xsd:element name="view" type="view_type" maxOccurs="unbounded"/>
+            </xsd:sequence>
+        </xsd:complexType>
+    
+    
+    <xsd:complexType name="banks_type">
+        <xsd:sequence>
+            <xsd:element name="bank" type="banktype" minOccurs="1" maxOccurs="12"/>
+        </xsd:sequence>
+    </xsd:complexType>
+    
+    <xsd:complexType name="banktype">
+        <xsd:sequence>
+            <xsd:element name="bank_description" type="bank_description_t"/>
+            <xsd:element name="registers" type="registerstype" minOccurs="0" maxOccurs="1"/>
+        </xsd:sequence>
+    </xsd:complexType>
+    
+    <xsd:complexType name="bank_description_t">
+        <xsd:sequence>
+            <xsd:element name="adress" type="bank_adress_type"/>
+            <xsd:element name="bar" type="bar_type"/>
+            <xsd:element name="size" type="hexa_and_integer64_t"/>
+            <xsd:element name="protocol" type="xsd:string"/>
+            <xsd:element name="read_adress" type="hex64_t"/>
+            <xsd:element name="write_adress" type="hex64_t"/>
+            <xsd:element name="word_size" type="uint8_t"/>
+            <xsd:element name="endianess" type="endianess_type"/>
+            <xsd:element name="format" type="xsd:string"/>
+            <xsd:element name="name" type="xsd:string"/>
+            <xsd:element name="description" type="xsd:string" minOccurs="0" maxOccurs="1"/>
+        </xsd:sequence>
+    </xsd:complexType>
+    
+    
+    <xsd:complexType name="registerstype">
+        <xsd:sequence>
+            <xsd:element name="register" type="register_type" minOccurs="0" maxOccurs="256"/>
+        </xsd:sequence>
+    </xsd:complexType>
+    
+    <xsd:complexType name="register_type">
+        <xsd:sequence>
+            <xsd:element name="adress" type="hexa_and_integer32_t"/>
+            <xsd:element name="offset" type="uint8_t"/>
+            <xsd:element name="size" type="uint8_t"/>
+            <xsd:element name="default" type="hexa_and_integer32_t"/>
+            <xsd:element name="rwmask" type="rwmask_type"/>
+            <xsd:element name="mode" type="pcilib_register_mode_t"/>
+            <xsd:element name="name" type="xsd:string"/>
+            <xsd:element name="description" type="xsd:string" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="views" type="reg_to_views_type" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="registers_bits" type="registers_bits_type" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="value_min" type="hexa_and_integer32_t" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="value_max" type="hexa_and_integer32_t" minOccurs="0" maxOccurs="1"/>
+          </xsd:sequence>
+    </xsd:complexType>
+    
+    <xsd:complexType name="registers_bits_type">
+        <xsd:sequence>
+            <xsd:element name="register_bits" type="register_bits_type" minOccurs="1" maxOccurs="32"/>
+        </xsd:sequence>
+    </xsd:complexType>
+    
+    <xsd:complexType name="reg_to_views_type">
+        <xsd:sequence>
+            <xsd:element name="view" type="xsd:string" minOccurs="1" maxOccurs="unbounded"/>
+        </xsd:sequence>
+    </xsd:complexType>
+    
+    <xsd:complexType name="register_bits_type">
+        <xsd:sequence>
+            <xsd:element name="offset" type="uint8_t"/>
+            <xsd:element name="size" type="uint8_t"/>
+            <xsd:element name="mode" type="pcilib_register_mode_t"/>
+            <xsd:element name="name" type="xsd:string"/>
+            <xsd:element name="description" type="xsd:string" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="views" type="reg_to_views_type" minOccurs="0" maxOccurs="1"/>
+        </xsd:sequence>
+
+    </xsd:complexType>
+    
+    <xsd:simpleType name="uint8_t">
+        <xsd:restriction base="xsd:integer">
+            <xsd:minInclusive value="0"/>
+            <xsd:maxInclusive value="255"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="size_t">
+        <xsd:restriction base="xsd:integer">
+            <xsd:minInclusive value="0"/>
+            <xsd:maxInclusive value="18446744073709551615"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="uintptr_t">
+        <xsd:restriction base="xsd:integer">
+            <xsd:minInclusive value="0"/>
+            <xsd:maxInclusive value="18446744073709551615"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="uint32_t">
+        <xsd:restriction base="xsd:integer">
+            <xsd:minInclusive value="0"/>
+            <xsd:maxInclusive value="4294967295"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="pcilib_register_mode_t">
+        <xsd:restriction base="xsd:string">
+            <xsd:enumeration value="R"/>
+            <xsd:enumeration value="W"/>
+            <xsd:enumeration value="RW"/>
+            <xsd:enumeration value="W1C"/>
+            <xsd:enumeration value="RW1C"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="bank_adress_type">
+        <xsd:restriction base="xsd:string">
+            <xsd:enumeration value="bank 0"/>
+            <xsd:enumeration value="bank 1"/>
+            <xsd:enumeration value="bank 2"/>
+            <xsd:enumeration value="bank 3"/>
+            <xsd:enumeration value="DMA bank"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="endianess_type">
+        <xsd:restriction base="xsd:string">
+            <xsd:enumeration value="little"/>
+            <xsd:enumeration value="big"/>
+            <xsd:enumeration value="host"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="bar_type">
+        <xsd:restriction base="xsd:integer">
+            <xsd:enumeration value="0"/>
+            <xsd:enumeration value="1"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="space_adress_type">
+        <xsd:restriction base="xsd:string">
+            <xsd:enumeration value="write adress"/>
+            <xsd:enumeration value="read adress"/>
+            <xsd:enumeration value="space adress"/>
+            <xsd:enumeration value="0"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="rwmask_type">
+        <xsd:restriction base="xsd:string">
+            <xsd:enumeration value="all bits"/>
+            <xsd:enumeration value="0"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="hexa_and_integer32_t">
+        <xsd:union memberTypes="uint32_t hex32_t"/>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="hex32_t">
+        <xsd:restriction base="xsd:string">
+            <xsd:pattern value="0x([a-fA-F0-9]){0,8}"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="hexa_and_integer64_t">
+        <xsd:union memberTypes="size_t hex64_t"/>
+    </xsd:simpleType>
+    
+    <xsd:simpleType name="hex64_t">
+        <xsd:restriction base="xsd:string">
+            <xsd:pattern value="0x([a-fA-F0-9]){0,16}"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+    <xsd:complexType name="view_type">
+        <xsd:sequence>
+            <xsd:element name="name" type="xsd:ID"/>
+            <xsd:element name="unit" type="xsd:string" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="read_from_register" type="xsd:string" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="write_to_register" type="xsd:string" minOccurs="0" maxOccurs="1"/>
+            <xsd:element name="enum" type="enum_t" minOccurs="0" maxOccurs="unbounded"/>
+	    <xsd:element name="description" type="xsd:string"/>
+	</xsd:sequence>
+        <xsd:attribute name="type" type="viewtype_type" use="required"/>
+    </xsd:complexType>
+    
+	<xsd:complexType name="enum_t">
+		<xsd:simpleContent>
+			<xsd:extension base="xsd:string">
+				<xsd:attribute name="value" type="hexa_and_integer64_t" use="required"/>
+       			<xsd:attribute name="min" type="hexa_and_integer64_t"/>
+		        <xsd:attribute name="max" type="hexa_and_integer64_t"/>
+			</xsd:extension>
+		</xsd:simpleContent>
+	</xsd:complexType>
+
+    <xsd:simpleType name="viewtype_type">
+        <xsd:restriction base="xsd:string">
+            <xsd:enumeration value="enum"/>
+            <xsd:enumeration value="formula"/>
+        </xsd:restriction>
+    </xsd:simpleType>
+    
+</xsd:schema>