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| author | Suren A. Chilingaryan <csa@suren.me> | 2016-02-23 07:20:33 +0100 |
|---|---|---|
| committer | Suren A. Chilingaryan <csa@suren.me> | 2016-02-23 07:20:33 +0100 |
| commit | a962c90543955bac98308c1b0d909048070d900a (patch) | |
| tree | 70b06851187e6bf8cfd8ee28931bdea25ea92ac7 /xml/test/test_prop3.py | |
| parent | 055279e09c3db9429e02874ec9620b9af357c80a (diff) | |
| parent | 52eb7f4fb76ddf99dedf44332aae7af4df76ab36 (diff) | |
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Merge Python scripting support from Vasiliy Chernov
Diffstat (limited to 'xml/test/test_prop3.py')
| -rw-r--r-- | xml/test/test_prop3.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/xml/test/test_prop3.py b/xml/test/test_prop3.py new file mode 100644 index 0000000..a082096 --- /dev/null +++ b/xml/test/test_prop3.py @@ -0,0 +1,5 @@ +def read_from_register(ctx, value): + return ctx.get_property('/registers/fpga/reg1') + +def write_to_register(ctx, value): + ctx.set_property(value, '/registers/fpga/reg1') |