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* Big redign of model structuresSuren A. Chilingaryan2015-04-201-3/+1
* Check for free space in camera DDR buffer before triggering eventSuren A. Chilingaryan2012-07-271-1/+2
* multithread preprocessing of ipecamera frames and code reorganizationSuren A. Chilingaryan2011-12-121-16/+24
* new event architecture, first trialSuren A. Chilingaryan2011-12-081-1/+2
* Improvements of DMA engineSuren A. Chilingaryan2011-10-261-1/+2
* Implement DMA access synchronization in the driverSuren A. Chilingaryan2011-07-161-0/+1
* Allow access to implementation context and provide call to set size of intern...Suren A. Chilingaryan2011-04-121-0/+1
* Prototype of IPECamera image protocolSuren A. Chilingaryan2011-04-121-0/+2
* Infrastructure for event APISuren A. Chilingaryan2011-04-121-0/+1
* Support for FPGA registersSuren A. Chilingaryan2011-03-091-0/+1
* Better handling of register banksSuren A. Chilingaryan2011-03-091-1/+2
* Initial support of IPECamera protocolSuren A. Chilingaryan2011-03-081-0/+16