Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Reorganization of NWL engine, step 1 | Suren A. Chilingaryan | 2011-07-11 | 4 | -128/+171 |
* | Wait for the completion of DMA operations during writes | Suren A. Chilingaryan | 2011-07-11 | 3 | -321/+335 |
* | IRQ support in NWL DMA engine | Suren A. Chilingaryan | 2011-07-11 | 7 | -129/+244 |
* | Support dynamic registers, support register offsets and multiregisters (bitma... | Suren A. Chilingaryan | 2011-07-09 | 2 | -8/+161 |
* | Add some check to verify if NWL DMA engine have been successfully initialized | Suren A. Chilingaryan | 2011-07-08 | 1 | -5/+3 |
* | Support alignments in kmem allocation | Suren A. Chilingaryan | 2011-07-06 | 1 | -1/+1 |
* | A bit of renaming | Suren A. Chilingaryan | 2011-07-06 | 2 | -12/+12 |
* | Define addresses of NWL engines | root | 2011-07-04 | 1 | -1/+3 |
* | North West Logick DMA implementation | root | 2011-07-04 | 3 | -104/+711 |
* | DMA engine initialization and basic intrastructure for DMA read/write | root | 2011-06-18 | 2 | -1/+102 |
* | Enumerate DMA engines | root | 2011-06-17 | 2 | -0/+208 |