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authorSuren A. Chilingaryan <csa@dside.dyndns.org>2012-07-24 15:47:34 +0200
committerSuren A. Chilingaryan <csa@dside.dyndns.org>2012-07-24 15:47:34 +0200
commit8643089a3d39b49115c547c3b9c27c0086754ec5 (patch)
treed08adf18760325c40cfab8134a8e3b8e9518fbc2 /ipecamera
parentf836cce5a89e5757111c6962bd8fa308d0685959 (diff)
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Support for new ufodecode and updated register model in ipecamera
Diffstat (limited to 'ipecamera')
-rw-r--r--ipecamera/data.c4
-rw-r--r--ipecamera/model.h47
-rw-r--r--ipecamera/private.h2
3 files changed, 41 insertions, 12 deletions
diff --git a/ipecamera/data.c b/ipecamera/data.c
index ff0813c..d753d43 100644
--- a/ipecamera/data.c
+++ b/ipecamera/data.c
@@ -37,8 +37,8 @@ static int ipecamera_resolve_event_id(ipecamera_t *ctx, pcilib_event_id_t evid)
inline static int ipecamera_decode_frame(ipecamera_t *ctx, pcilib_event_id_t event_id) {
int err = 0;
size_t res;
- uint32_t tmp;
uint16_t *pixels;
+ UfoDecoderMeta meta;
int buf_ptr = ipecamera_resolve_event_id(ctx, event_id);
if (buf_ptr < 0) return PCILIB_ERROR_TIMEOUT;
@@ -54,7 +54,7 @@ inline static int ipecamera_decode_frame(ipecamera_t *ctx, pcilib_event_id_t eve
pixels = ctx->image + buf_ptr * ctx->image_size;
memset(ctx->cmask + ctx->buffer_pos * ctx->dim.height, 0, ctx->dim.height * sizeof(ipecamera_change_mask_t));
- res = ufo_decoder_decode_frame(ctx->ipedec, ctx->buffer + buf_ptr * ctx->padded_size, ctx->raw_size, pixels, &tmp, &tmp, &tmp, ctx->cmask + ctx->buffer_pos * ctx->dim.height);
+ res = ufo_decoder_decode_frame(ctx->ipedec, ctx->buffer + buf_ptr * ctx->padded_size, ctx->raw_size, pixels, &meta);
if (!res) {
ctx->frame[buf_ptr].event.image_broken = 1;
err = PCILIB_ERROR_FAILED;
diff --git a/ipecamera/model.h b/ipecamera/model.h
index 31aa01c..3899acc 100644
--- a/ipecamera/model.h
+++ b/ipecamera/model.h
@@ -75,17 +75,46 @@ pcilib_register_description_t ipecamera_registers[] = {
{0x00, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_input", ""},
{0x10, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_conf_output", ""},
{0x20, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "spi_clk_speed", ""},
-{0x30, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_version", ""},
+{0x30, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "firmware_info", ""},
+{0x30, 0, 8, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "firmware_version", ""},
+{0x30, 8, 1, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "firmware_bitmode", ""},
+{0x30, 12, 2, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "adc_resolution", ""},
+{0x30, 16, 2, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "output_mode", ""},
{0x40, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "control", ""},
{0x50, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status", ""},
-{0x60, 0, 16, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "cmosis_temperature", ""},
-{0x70, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_sample_timing", ""},
-{0x80, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_address", ""},
-{0x90, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "end_address", ""},
-{0x100, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "last_write_address", ""},
-{0x110, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status3", ""},
-{0x160, 0, 32, 0, 0, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "reg9160", ""},
-{0x170, 0, 32, 0, 0, PCILIB_REGISTER_R , PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "reg9170", ""},
+{0x54, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status2", ""},
+{0x58, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "status3", ""},
+{0x5c, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_status", ""},
+{0x70, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "start_address", ""},
+{0x74, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "end_address", ""},
+{0x78, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rd_address", ""},
+{0xa0, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param1", ""},
+{0xa0, 0, 11, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_skip_lines", ""},
+{0xa0, 11, 11, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_num_lines", ""},
+{0xa0, 22, 10, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_start_address", ""},
+{0xb0, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "fr_param2", ""},
+{0xa0, 0, 11, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fr_threshold_lines", ""},
+{0xc0, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "skiped_lines", ""},
+{0x100, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "rawdata_pkt_addr", ""},
+{0x110, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_info", ""},
+{0x110, 0, 19, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "sensor_temperature", ""},
+{0x110, 19, 10, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "fpga_temperature", ""},
+{0x110, 29, 3, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "temperature_alarms", ""},
+{0x120, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "copy_num_lines", ""},
+{0x130, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "copy_start_line", ""},
+{0x140, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "copy_exp_time", ""},
+{0x150, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "motor", ""},
+{0x150, 0, 5, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_phi", ""},
+{0x150, 5, 5, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_z", ""},
+{0x150, 10, 5, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_y", ""},
+{0x150, 15, 5, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "motor_x", ""},
+{0x150, 20, 8, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_BITS, PCILIB_REGISTER_BANK1, "copy_adc_gain", ""},
+{0x160, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "write_status", ""},
+{0x170, 0, 32, 0, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_triggers", ""},
+{0x180, 0, 32, 0x280, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "trigger_period", ""},
+{0x190, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "temperature_sample_period", ""},
+{0x1a0, 0, 32, 0x64, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "max_frames", ""},
+{0x1b0, 0, 32, 0, 0, PCILIB_REGISTER_R, PCILIB_REGISTER_STANDARD, PCILIB_REGISTER_BANK1, "num_frames", ""},
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL}
};
diff --git a/ipecamera/private.h b/ipecamera/private.h
index 34eb99a..a0fb4e4 100644
--- a/ipecamera/private.h
+++ b/ipecamera/private.h
@@ -55,7 +55,7 @@ typedef struct {
struct ipecamera_s {
pcilib_context_t event;
- ufo_decoder ipedec;
+ UfoDecoder *ipedec;
char *data;
ipecamera_pixel_t *image;