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authorVasilii Chernov <vchernov@inr.ru>2016-02-09 17:32:11 +0100
committerVasilii Chernov <vchernov@inr.ru>2016-02-09 17:32:11 +0100
commitdce856c1a16098fe7a1df2338df60073261da94a (patch)
tree61285a125a21bd311c3835f8b0fb8a7cc94d8f76 /pcitool/cli.c
parentaaac7b80d1e003a3dbc4fe0f831a68e5449c846d (diff)
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Add write_register python wrap. Add no_set_check attribute to pcilib_view_t type
Diffstat (limited to 'pcitool/cli.c')
-rw-r--r--pcitool/cli.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/pcitool/cli.c b/pcitool/cli.c
index 8350d24..cb87dcb 100644
--- a/pcitool/cli.c
+++ b/pcitool/cli.c
@@ -1702,10 +1702,12 @@ int WriteRegister(pcilib_t *handle, const pcilib_model_description_t *model_info
if ((model_info->registers[regid].mode&PCILIB_REGISTER_RW) == PCILIB_REGISTER_RW) {
const char *format = (val.format?val.format:"%u");
+
err = pcilib_read_register(handle, bank, reg, &verify);
if (err) Error("Error reading back register %s for verification\n", reg);
-
- if (verify != value) {
+
+ if (!((model_info->registers[regid].mode&PCILIB_REGISTER_NO_CHK) == PCILIB_REGISTER_NO_CHK) &&
+ verify != value) {
Error("Failed to write register %s: %lu is written and %lu is read back", reg, value, verify);
} else {
printf("%s = ", reg);